As electronic devices such as personal computers, lap top computers, video cameras, hand-held data readers and other similar devices become increasingly complex, the amount of information which must be internally communicated among components has also significantly increased. For example, disk drive controllers, such as SCSI controllers, network interface cards (NICs), display controllers, and video graphic boards all must communicate with a host processor which acts as a central controller for the particular electronic device. Each component, or peripheral device, attempts to send information to a local bus associated with the host processor in order to communicate its messages. To handle the large number of peripheral devices, standard bus configurations have been developed to interface the peripheral devices with the local bus. An arbitration scheme is then used to prioritize which peripheral device should have access to the standard bus (i.e. be the bus master) at any given time so that data collisions between two or more peripheral devices attempting to communicate with the host processor are avoided.
The arbitration scheme is typically handled by an arbiter whose function is to receive bus request signals from devices wishing to communicate over the standard bus and then schedule when each device will gain such access. For example, one commonly known bus configuration to which peripheral devices would directly connect is the ISA bus. The ISA bus design allows an arbiter to use a Direct Memory Accessing (DMA) scheme to process and prioritize requests to use the ISA bus. The ISA bus, however, is limited in its ability to transfer high density data at fast rates and therefore new standard bus configurations are being developed.
Among the more popular of the newer standard bus configurations is the Peripheral Component Interconnect (PCI) bus. The PCI bus has many advantageous over the ISA bus in its ability to communicate data at a significantly faster rate. However, based on its design, the PCI bus no longer allows the associated bus arbiter to use a DMA scheme in prioritizing bus requests and therefore hardware prioritization schemes are being developed. For instance, some PCI bus arbiters are designed to give lowest priority to those devices which most recently requested and received permission to communicate over the PCI bus. However, as is pointed out in U.S. Pat. No. 5,471,590, this prioritization scheme has drawbacks in situations where a particular device has gained access to the bus and the host processor but needs to retry its communication due to some mishap. More specifically, although the original device was of high enough priority to gain access to the bus and host processor, the arbiter would automatically re-assign a low priority to this device even though the message never was properly passed along and processed.
The arbitration scheme described in the aforementioned U.S. Pat. No. 5,471,590 describes a system which reduces this problem by providing an arbiter which does not change the priority level of devices which must retry. Although this may be an improvement over known arbitration schemes, both of these schemes still have major drawbacks. More particularly, since devices cannot ever increase from their preset priority value, those devices with low priority may rarely have an opportunity to access the bus in a busy system. Unfortunately, even with a low initial priority rating such devices do eventually need access to the bus to avoid buffer overflow situations and other similar problems.
In view of the aforementioned shortcomings associated with conventional arbiters and arbitration methods, there is a strong need in the art for an arbiter and method which prioritizes access to a bus taking into account the concerns discussed above. In particular, there is a strong need in the art for an arbiter and method which better allocates bus access such that all devices may receive the bus regardless of their preset priority level or the amount of traffic in the system.